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--This module is a simple 32-bit counter, with an asynchronous reset
--
--Oussama Chammam, IC-control-localization-project team
--KTH, MF2063
--last edit: 2012-11-15
----------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.all;
----------------------------------------

entity counter is
	port(	
			clk : in std_logic;
			reset : in std_logic;
			
			counter : out std_logic_vector(31 downto 0)
		);
end counter;


architecture behaviour of counter is
signal counter_buffer : std_logic_vector(31 downto 0);

begin

	counter <= counter_buffer;
	
	process(clk, reset)
	begin
		if reset = '1' then 									--assynchronous reset
			counter_buffer <= x"00000000";			
		elsif rising_edge(clk) then
			counter_buffer <= counter_buffer +1;
		end if;
	
	end process;
end behaviour;

